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single/dual, +15 v/5 v, 256-position, i 2 c-compatible digital potentiometer ad5280/ad5282 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2007 analog devices, inc. all rights reserved. features ad5280: 1 channel ad5282: 2 channels 256 positions 5 v to 15 v single supply; 5.5 v dual-supply operation fixed terminal resistance: 20 k, 50 k, 200 k low temperature coefficient: 30 ppm/c power-on midscale preset 1 programmable reset operating temperature: ?40 o c to +85 o c i 2 c-compatible interface applications multimedia, video, and audio communications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage source programmable current source line impedance matching general description the ad5280/ad5282 are single-channel and dual-channel, 256-position, digitally controlled variable resistors (vrs) 2 . the devices perform the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. each vr offers a completely programmable value of resistance between the a terminal and the wiper or the b terminal and the wiper. the fixed a-to-b terminal resistance of 20 k, 50 k, or 200 k has a 1% channel-to-channel matching tolerance. the nominal temperature coefficient of both parts is 30 parts per million/ degrees centigrade (ppm/c). another key feature is that the parts can operate up to +15 v or 5 v. wiper position programming defaults to midscale at system power-on. when powered, the vr wiper position is programmed by an i 2 c-compatible, 2-wire serial data interface. the ad5280/ ad5282 feature sleep mode programmability. this allows any level of preset in power-up and is an alternative to a costly eeprom solution. both parts have additional programmable logic outputs that enable users to drive digital loads, logic gates, led drivers, and analog switches in their system. 1 assert shutdown and program the device during power-up, then deassert the shutdown to achieve the desired preset level. 2 the terms digital potentiometer, vr, and rdac are used interchangeably. the ad5280/ad5282 are available in thin, surface-mounted 14-lead tssop and 16-lead tssop. all parts are guaranteed to operate over the extended industrial temperature range of ?40c to +85c. for 3-wire spi-compatible interface applica- tions, see the ad5260 / ad5262 product information on www.analog.com . functional block diagrams a wb o 1 o 2 rdac register output register serial input register ad5280 s hdn v dd v ss sda scl gnd ad0 ad1 address code pwr on reset v l 8 02929-070 figure 1. ad5280 a 1 w 1 b 1 o 1 rdac1 register rdac2 register output register serial input register ad5282 shdn v dd sda scl gnd ad0 ad1 address code pwr on reset a 2 w 2 b 2 8 02929-001 v dd v ss v l figure 2. ad5282
ad5280/ad5282 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagrams............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics............................................................. 3 absolute maximum ratings............................................................ 5 thermal resistance ...................................................................... 5 esd caution.................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 test circuits..................................................................................... 12 theory of operation ...................................................................... 14 rheostat operation .................................................................... 14 potentiometer operation........................................................... 14 digital interface .............................................................................. 16 2-wire serial bus........................................................................ 16 readback rdac value .............................................................. 17 additional programmable logic output ................................ 17 self-contained shutdown function and programmable preset ............................................................................................ 17 multiple devices on one bus ................................................... 17 level shift for bidirectional interface...................................... 18 level shift for negative voltage operation ............................ 18 esd protection ........................................................................... 18 terminal voltage operating range ......................................... 18 power-up sequence ................................................................... 18 layout and power supply bypassing ....................................... 19 applications information .............................................................. 20 bipolar dc or ac operation from dual supplies................. 20 gain control compensation .................................................... 20 15 v, 8-bit i 2 c dac.................................................................... 20 8-bit bipolar dac ...................................................................... 21 bipolar programmable gain amplifier................................... 21 programmable voltage source with boosted output ........... 21 programmable current source ................................................ 22 programmable bidirectional current source......................... 22 programmable low-pass filter ................................................ 23 programmable oscillator .......................................................... 23 rdac circuit simulation model............................................. 24 macro model net list for rdac ............................................. 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 26 revision history 8/07rev. a to rev. b updated operating temperature range throughout ...................1 changes to the features section.......................................................1 changes to the general description section..................................1 changes to table 2..............................................................................3 added the thermal resistance section...........................................5 changes to the ordering guide......................................................26 11/05rev. 0 to rev. a updated format................................................................... universal updated outline dimensions .........................................................26 changes to ordering guide ............................................................27 10/02revision 0: initial version
ad5280/ad5282 rev. b | page 3 of 28 specifications electrical characteristics v dd = +15 v, v ss = 0 v or v dd = +5 v, v ss = ?5 v; v logic = 5 v, v a = +v dd , v b = 0 v; ?40c < t a < +85c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristicsCrheostat mode resistor differential nl 2 r-dnl r wb , v a = nc ?1 1/4 +1 lsb resistor nonlinearity 2 r-inl r wb , v a = nc ?1 1/4 +1 lsb nominal resistor tolerance 3 r ab t a = 25c ?30 +30 % resistance temperature coefficient (?r ab /r ab )/?t x 10 6 v ab = v dd , wiper = no connect 30 ppm/c wiper resistance r w i w = v dd /r, v dd = 3 v or 5 v 60 150 dc characteristicsCpotentiometer divider mode (specifications apply to all vrs) resolution n 8 bits integral nonlinearity 4 inl ?1 1/4 +1 lsb differential nonlinearity 4 dnl ?1 1/4 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t x 10 6 code = 0x80 5 ppm/c full-scale error v wfse code = 0xff ?2 ?1 0 lsb zero-scale error v wzse code = 0x00 0 +1 +2 lsb resistor terminals voltage range 5 v a , v b , v w v ss v dd v capacitance a, b 6 c a , c b f = 5 mhz, measured to gnd, code = 0x80 25 pf capacitance w 6 c w f = 1 mhz, measured to gnd, code = 0x80 55 pf common-mode leakage i cm v a = v b = v w 1 na shutdown current i shdn 5 a digital inputs and outputs input logic high v ih 0.7 v l v l + 0.5 v input logic low v il 0 0.3 v l v output logic high (o 1 , o 2 ) v ih 4.9 v output logic low (o 1 , o 2 ) v il 0.4 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies logic supply v logic 2.7 v dd v power single-supply range v dd range v ss = 0 v 4.5 16.5 v power dual-supply range v dd/ss range 4.5 5.5 v logic supply current i logic v logic = 5 v 60 a positive supply current i dd v ih = 5 v or v il = 0 v 0.1 1 a negative supply current i ss 0.1 1 a power dissipation 7 p diss v ih = 5 v or v il = 0 v, v dd = +5 v, v ss = ?5 v 0.2 0.3 mw power supply sensitivity pss 0.002 0.01 %/% dynamic characteristics 6 , 8 , 9 bandwidth ?3 db bw_20k r ab = 20 k, code = 0x80 310 khz bw_50k r ab = 50 k, code = 0x80 150 khz bw_200k r ab = 200 k, code = 0x80 35 khz
ad5280/ad5282 rev. b | page 4 of 28 parameter symbol conditions min typ 1 max unit total harmonic distortion thd w v a = 1 v rms, r ab = 20 k 0.014 % v b = 0 v dc, f = 1 khz v w settling time t s v a = 5 v, v b = 5 v, 1 lsb error band 5 s crosstalk ct v a = v dd , v b = 0 v, measure v w1 with adjacent rdac making full-scale code change 15 nv-s analog crosstalk cta measure v w1 with v w2 = 5 v p-p @ f = 10 khz ?62 db resistor noise voltage e n_wb r wb = 20 k, f = 1 khz 18 nv/hz interface timing characteristics (applies to all parts) 6 , 10 , 11 scl clock frequency f scl 0 400 khz t buf bus free time between stop and start t 1 1.3 s t hd:sta hold time (repeated start) t 2 after this period, the first clock pulse is generated 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su:sta setup time for start condition t 5 0.6 s t hd:dat data hold time t 6 0 0.9 s t su:dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su:sto setup time for stop condition t 10 0.6 s 1 typicals represent average readings at 25c, v dd = +5 v, v ss = ? 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed mono tonic operating conditions. 5 resistor terminal a, resistor terminal b, and wiper terminal w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 8 bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the f astest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 9 all dynamic characteristics use v dd = 5 v. 10 see timing diagram (f igure 3) for location of measured values. 11 standard i 2 c mode operation is guaranteed by design. 02929-042 t 1 t 2 t 3 t 8 t 8 t 9 t 9 t 6 t 4 t 7 t 5 t 2 t 10 ps s scl s da p figure 3. detailed timing diagram
ad5280/ad5282 rev. b | page 5 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 2. parameter rating v dd to gnd ?0.3 v to +16.5 v v ss to gnd 0 v to ?7 v v dd to v ss 16.5 v v a , v b , v w to gnd v ss to v dd a x to b x , a x to w x , b x to w x intermittent 3 20 ma continuous 5 ma v logic to gnd 0 v to 7 v output voltage to gnd 0 v to 7 v operating temperature range ?40c to +85c maximum junction temperature (t jmax ) 150c storage temperature range ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec 3 maximum terminal current is bound by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. package power dissipation = (t jmax ? t a )/ ja . table 3. thermal resistance package type ja unit tssop-14 206 c/w tssop-16 150 c/w esd caution
ad5280/ad5282 rev. b | page 6 of 28 pin configurations and function descriptions a w b shdn scl v dd sda 1 2 3 4 5 6 7 14 13 12 11 10 9 8 o 1 v l o 2 gnd ad1 v ss ad0 ad5280 top view 02929-002 figure 4. ad5280 pin configuration o 1 a 1 w 1 v dd shdn b 1 scl 1 2 3 4 5 6 7 sda 8 16 15 14 13 12 11 10 a 2 w 2 b 2 v ss gnd v l ad1 9 ad0 ad5282 top view 02929-003 figure 5. ad5282 pin configuration table 4. ad5280 pin function descriptions pin no. mnemonic description 1 a resistor terminal a. 2 w wiper terminal w. 3 b resistor terminal b. 4 v dd positive power supply. specified for operation from 5 v to 15 v (sum of |v dd | + |v ss | 15 v). 5 shdn active low, asynchronous connection of wiper w to terminal b and open circuit of terminal a. rdac register contents unchanged. shdn should tie to v l if not used. can also be used as a programmable preset in power-up. 6 scl serial clock input. 7 sda serial data input/output. 8 ad0 programmable address bit 0 for multiple package decoding. bit ad0 and bit ad1 provide four possible addresses. 9 ad1 programmable address bit 1 for multiple package decoding. bit ad0 and bit ad1 provide four possible addresses. 10 gnd common ground. 11 v ss negative power supply. specified for operation from 0 v to ?5 v (sum of |v dd | + |v ss | 15 v). 12 o 2 logic output terminal o 2. 13 v l logic supply voltage. needs to be less than or equal to v dd and at the same voltage as the digital logic controlling the ad5280. 14 o 1 logic output terminal o 1 . table 5. ad5282 pin function descriptions pin no. mnemonic description 1 o 1 logic output terminal o 1 . 2 a 1 resistor terminal a 1 . 3 w 1 wiper terminal w 1 . 4 b 1 resistor terminal b 1 . 5 v dd positive power supply. specified for operation from 5 v to 15 v (sum of |v dd | + |v ss | 15 v). 6 shdn active low, asynchronous connection of wiper w to terminal b and open circuit of terminal a. rdac register contents unchanged. shdn should tie to v l if not used. can be also used as a programmable preset in power-up. 7 scl serial clock input. 8 sda serial data input/output. 9 ad0 programmable address bit 0 for multiple package decoding. bit ad0 and bit ad1 provide four possible addresses. 10 ad1 programmable address bit 1 for multiple package decoding. bit ad0 and bit ad1 provide four possible addresses. 11 gnd common ground. 12 v ss negative power supply. specified for operation from 0 v to ?5 v (sum of |v dd | + |v ss | 15 v). 13 v l logic supply voltage. needs to be less than or equal to v dd and at the same voltage as the digital logic controlling the ad5282. 14 b 2 resistor terminal b 2 . 15 w 2 wiper terminal w 2 . 16 a 2 resistor terminal a 2 .
ad5280/ad5282 rev. b | page 7 of 28 typical performance characteristics code (decimal) rheostat mode r-inl (lsb) 1.0 0.8 0.6 0.4 0.2 ?0.2 ?0.6 ?0.8 0 ?0.4 ?1.0 0 32 96 160 224 64 128 192 256 02929-004 5v +15v +5v r ab = 20k ? t a = 25c figure 6. r-inl vs. code vs. supply voltages code (decimal) rheostat mode r-dnl (lsb) 0.5 0.4 0.3 0.2 0.1 ?0.1 ?0.3 ?0.8 0 ?0.2 ?0.5 0 32 96 160 224 64 128 192 256 02929-005 5v +15v +5v r ab = 20k ? t a = 25c figure 7. r-dnl vs. code vs. supply voltages code (decimal) potentiometer mode inl (lsb) 1.0 0.8 0.6 0.4 0.2 ?0.2 ?0.6 ?0.8 0 ?0.4 ?1.0 0 32 96 160 224 64 128 192 256 02929-006 t a = +85c t a = ?40c t a = +25c r ab = 20k ? figure 8. inl vs. code, v dd /v ss = 5 v code (decimal) potentiometer mode dnl (lsb) 0.5 0.4 0.3 0.2 0.1 ?0.1 ?0.3 ?0.4 0 ?0.2 ?0.5 0 32 96 160 224 64 128 192 256 02929-007 t a = ?40c t a = +85c t a = +25c r ab = 20k ? figure 9. dnl vs. code, v dd /v ss = 5 v code (decimal) potentiometer mode inl (lsb) 1.0 0.8 0.6 0.4 0.2 ?0.2 ?0.6 ?0.8 0 ?0.4 ?1.0 0 32 96 160 224 64 128 192 256 02929-008 5v +5v r ab = 20k ? t a = 25c +15v figure 10. inl vs. code vs. supply voltages code (decimal) potentiometer mode inl (lsb) 0.5 0.4 0.3 0.2 0.1 ?0.1 ?0.3 ?0.4 0 ?0.2 ?0.5 0 32 96 160 224 64 128 192 256 02929-009 r ab = 20k ? t a = 25c 5v +5v +15v figure 11. dnl vs. code vs. supply voltages
ad5280/ad5282 rev. b | page 8 of 28 |v dd ? v ss | (v) inl (lsb) 1.0 0.5 ?0.5 0 ?1.0 0 5 10 15 20 02929-010 r ab = 20k ? t a = 25c avg +3 avg avg ?3 figure 12. inl over supply voltage |v dd ? v ss | (v) r-inl (lsb) 2.0 1.0 1.5 0.5 ?1.0 ?0.5 ?1.5 0 ?2.0 0 5 10 15 20 02929-011 r ab = 20k ? t a = 25c avg +3 avg avg ?3 figure 13. r-inl over supply voltage temperature (c) full-scale error (lsb) 0 ?0.4 ?0.2 ?0.8 ?0.6 ?1.6 ?1.2 ?1.4 ?1.8 ?1.0 ?2.0 ?40 0 ?20 20 40 60 80 100 02929-012 r ab = 20k ? v dd /v ss = +15v/0v v dd /v ss = +5v/0v v dd /v ss = 5v figure 14. full-scale error temperature (c) zero-scale error (lsb) 2.0 1.6 1.8 1.2 1.4 0.4 0.8 0.6 0.2 1.0 0 ?40 0 ?20 20 40 60 80 100 02929-013 r ab = 20k ? v dd /v ss = +15v/0v v dd /v ss = +5v/0v v dd /v ss = 5v figure 15. zero-scale error temperature (c) i dd /i ss supply current (na) 1000 100 10 1 ?40 ?7 26 59 85 02929-014 | dd @v dd /v ss = 5v r ab = 20k ? v logic = +5v v ih = +5v v il = 0v | ss @v dd /v ss = 5v | ss @v dd /v ss = +15v/0v figure 16. supply current vs. temperature temperature (c) i logic (a) 26.0 25.0 24.0 23.5 24.5 25.5 23.0 ?40 ?7 26 59 85 02929-015 v dd /v ss = 5v v dd /v ss = +15v/0v r ab = 20k ? figure 17. v logic supply current vs. temperature
ad5280/ad5282 rev. b | page 9 of 28 5 v ih (v) i logic (a) 1000 100 10 01234 02929-016 r ab = 20k ? t a = 25c v dd /v ss = 5v/0v v logic = 3v v dd /v ss = 5v/0v v logic = 5v figure 18. v logic supply current vs. digital input voltage code (decimal) rheost a t mode tempco (ppm/c) 700 300 400 500 600 200 100 0 ?100 ?200 0 32 64 192 96 128 224 256 02929-017 t a = 25c 20k ? 50k ? 200k ? figure 19. rheostat mode tempco r wb / t vs. code, v dd /v ss = 5 v code (decimal) potentiometer mode tempco (ppm/c) 120 40 60 80 100 20 0 ?20 ?40 0 32 64 192 96 128 224 256 02929-018 t a = 25c 20k ? 50k ? 200k ? figure 20. potentiometer mode tempco v wb / t vs. code, v dd /v ss = 5 v frequency (hz) gain (db) 0 ?30 ?24 ?12 ?18 ?6 ?36 ?48 ?42 ?54 ?60 0 10k 100k 1m 02929-019 t a = 25c v a = 50mv rms v dd /v ss = 5v 80h 20h 10h 08h 04h 02h 01h 40h figure 21. gain vs. frequency vs. code, r ab = 20 k frequency (hz) gain (db) 0 ?30 ?24 ?12 ?18 ?6 ?36 ?48 ?42 ?54 ?60 0 10k 100k 1m 02929-020 t a = 25c v a = 50mv rms v dd /v ss = 5 80h 20h 10h 08h 04h 02h 01h 40h figure 22. gain vs. frequency vs. code, r ab = 50 k frequency (hz) gain (db) 0 ?30 ?24 ?12 ?18 ?6 ?36 ?48 ?42 ?54 ?60 0 10k 100k 1m 02929-021 t a = 25c v a = 50mv rms v dd /v ss = 5v 80h 20h 10h 08h 04h 02h 01h 40h figure 23. gain vs. frequency vs. code, r ab = 200 k
ad5280/ad5282 rev. b | page 10 of 28 frequency (hz) gain (db) 0 ?30 ?24 ?12 ?18 ?6 ?36 ?48 ?42 ?54 ?60 0 10k 100k 1m 02929-022 t a = 25c v dd /v ss = 5v v a = 50mv rms r = 20k ? 310khz r = 50k ? 150khz r = 200k ? 35khz figure 24. ? 3 db bandwidth frequency (hz) nominalized gain fl a tness (0.1db/div) ?6db 100 1k 10k 100k 02929-023 t a = 25c v dd /v ss = 5v r = 200k ? r = 20k ? r = 50k ? figure 25. normalized gain flatness vs. frequency frequency (hz) i logic ( m a) 500 300 400 200 100 0 10k 100k 1m 10m 02929-024 t a = 25c v dd /v ss = 5v code = 55 h code = 55 h figure 26. v logic supply current vs. frequency frequency (mhz) psrr (db) 80 40 60 20 0 100 1000 10k 100k 1m 02929-025 code = 80 h , v a = v dd , v b = 0v +psrr @ v dd /v ss = 5v dc 10% p-p ac ?psrr @ v dd /v ss = 5v dc 10% p-p ac figure 27. psrr vs. frequency 02929-026 a2 1.2v 852.0s 2.04s figure 28. midscale glitch energy code 0x80 to 0x7f 02929-027 ch1 5.00v ch2 5.00v m100ns a ch1 0v v w cs 2 1 +5v ?5v t figure 29. large signal settling time
ad5280/ad5282 rev. b | page 11 of 28 02929-028 a2 1.0v 33.41s 1.50s figure 30. digital feedthrough vs. time code (decimal) theoretic a l | wb_max (ma) 100 0.1 1.0 10 0.01 0 32 64 192 96 128 224 256 02929-029 v a = v b = open t a = 25c r ab = 20k ? r ab = 50k ? r ab = 200k ? figure 31. i wb_max vs. code long term channel-to-channel rab match (%) frequen c y (mhz) 40 10 20 30 0 ?0.5 ?0.45 ?0.4 ?0.35 ?0.3 ?0.25 ?0.2 ?0.15 ?0.1 0.2 0.15 0.1 0.05 0 ?0.05 02929-030 codes set to midscale 3 lots sample size = 135 figure 32. channel-to-channel resistance matching (ad5282)
ad5280/ad5282 rev. b | page 12 of 28 test circuits figure 33 to figure 43 define the test conditions used in the product specification table. a w b dut v+ = v dd 1lsb = v+/2 n v+ v ms 02929-031 figure 33. potentiometer divider nonlinearity error (inl, dnl) a w b dut i w no connect v ms 02929-032 figure 34. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) a w b dut v ms2 v ms1 v w 02929-033 i w = v dd /r nominal r w = [v ms1 ?v ms2 ]/i w figure 35. wiper resistance a w b v dd v a v+ v ms 02929-034 v + = v dd 10 % psrr (db) = 20 log ( ) pss (%/%) = v ms v dd v ms % v dd % figure 36. power supply sensitivity (pss, pssr) w dut a 5v v ou t offset gnd offset bias v in 02929-035 op279 b figure 37. inverting gain w v ou t offset gnd offset bias v in 02929-036 dut op279 5 v b a figure 38. noninverting gain v out offset gnd 2.5v v in dut 02929-037 a w ad8610 +15v ?15v b figure 39. gain vs. frequency w b v ss to v dd dut i sw 0.1v r sw = 0.1 v i sw 02929-038 figure 40. incremental on resistance
ad5280/ad5282 rev. b | page 13 of 28 w b v cm i cm a nc gnd nc v ss v dd dut nc = no connect 02929-039 figure 41. common-mode leakage current scl i logic v logic sca digital input voltage 0 2929-040 figure 42. v logic current vs. digital input voltage n/c rdac 1 w 1 b 1 v ss v dd a 2 rdac 2 w 2 b 2 v out a 1 v in c ta = 20 log [v out /v in ] 02929-041 figure 43. analog crosstalk (ad5282 only)
ad5280/ad5282 rev. b | page 14 of 28 theory of operation the ad5280/ad5282 are single-channel and dual-channel, 256-position, digitally controlled variable resistors (vrs). to program the vr settings, see the digital interface section. both parts have an internal power-on preset that places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. operation of the power-on preset function also depends on the state of the v l pin. d7 d6 d5 d4 d3 d2 d1 d0 rdac latch and decoder r s r s r s a x w x b x r s shdn 0xff 0x01 sw b sw a 0x00 02929-045 figure 44. ad5280/ad5282 equivalent rdac circuit rheostat operation the nominal resistance of the rdac between terminal a and terminal b is available in 20 k, 50 k, and 200 k. the final two or three digits of the part number determine the nominal resistance value, for example, 20 k = 20, 50 k = 50, and 200 k = 200. the nominal resistance (r ab ) of the vr has 256 contact points accessed by the wiper terminal, plus the b terminal contact. the eight-bit data in the rdac latch is decoded to select one of the 256 possible settings. assuming that a 20 k part is used, the wipers first connection starts at the b terminal for data 0x00. because there is a 60 wiper contact resistance, such a connection yields a minimum of 60 resistance between terminal w and terminal b. the second connection is the first tap point that corresponds to 138 (r wb = r ab /256 + r w = 78 + 60 ) for data 0x01. the third connection is the next tap point representing 216 (78 2 + 60) for data 0x02, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 19,982 (r ab C 1 lsb + r w ). figure 46 shows a simplified diagram of the equivalent rdac circuit where the last resistor string is not accessed; therefore, there is 1 lsb less of the nominal resistance at full scale in addition to the wiper resistance. the general equation determining the digitally programmed output resistance between w and b is () += 256 (1) where: d is the decimal equivalent of the binary code loaded in the 8- bit rdac register. r ab is the nominal end-to-end resistance. r w is the wiper resistance contributed by the on resistance of the internal switch. note that in the zero-scale condition, a finite wiper resistance of 60 is present. care should be taken to limit the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. as in the mechanical potentiometer, the resistance of the rdac between wiper w and terminal a also produces a digitally controlled complementary resistance, r wa . when these terminals are used, the b terminal can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is () + ? = 256 256 (2) the typical distribution of the nominal resistance, r ab , from channel to channel matches within 1%. device-to-device matching is process lot dependent, and it is possible to have a 30% variation. because the resistance element is processed in thin film technology, the change in r ab with temperature is very small (30 ppm/c). potentiometer operation the digital potentiometer easily generates a voltage divider at wiper to b and wiper to a to be proportional to the input voltage at a to b. unlike the polarity of v dd C v ss , which must be positive, voltage across a to b, w to a, and w to b can be at either polarity, provided that v ss is powered by a negative supply. if the effect of the wiper resistance for approximation is ignored, connecting the a terminal to 5 v and the b terminal to ground produces an output voltage at the wiper to b starting at 0 v up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across a to b divided by the 256 positions of the potentiometer divider. because the ad5280/ad5282 can be supplied by dual supplies, the general equation defining the output voltage at v w with respect to ground for any valid
ad5280/ad5282 rev. b | page 15 of 28 input voltage applied to terminal a and terminal b is () b a w v d v d dv 256 256 256 ? += (3) for a more accurate calculation that includes the effect of wiper resistance, v w can be found as () () () b ab wa a ab wb w v r dr v r dr dv + = (4) operation of the digital potentiometer in divider mode results in a more accurate operation over temperature. unlike rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors r wa and r wb and not on the absolute values; therefore, the temperature drift reduces to 5 ppm/c. 19 1 1 99 scl sda start by master frame 1 slave address byte ack. by ad5280/5282 frame 2 instruction byte ack. by ad5280/ad5282 frame 3 data byte ack. by ad5280/5282 stop by master 01011 ad1 r/w a/brssdo1o2 x x x d7d6d5d4d3d2d1d0 ad0 02929-043 figure 45. writing to the rdac register 1 91 9 scl sda start by master frame 1 slave address byte ack. by ad5280/ad5282 frame 2 data byte from previously selected no ack. by master stop by master 0 1 0 1 1ad1ad0r/w d7d6d5d4d3d2d1d0 a 02929-044 figure 46. reading data from a previously selected rdac register in write mode table 6. serial format of data accepted from the i 2 c bus s 0 1 0 1 1 ad1 ad0 r/ w a a /b rs sd o 1 o 2 x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte where: abbreviation equals s start condition p stop condition a acknowledge x dont care ad1, ad0 package pin programmable address bits r/ w read enable at high and write enable at low a /b rdac subaddress select; 0 = rdac1 and 1 = rdac2 rs midscale reset, active high (only affects selected channel) sd shutdown; same as shdn pin operation except inverse logic (only affects selected channel) o 2 , o 1 output logic pin latched values; default logic 0 d7, d6, d5, d4, d3, d2, d1, d0 data bits
ad5280/ad5282 rev. b | page 16 of 28 digital interface 2-wire serial bus the ad5280/ad5282 are controlled via an i 2 c-compatible serial bus. the rdacs are connected to this bus as slave devices. as shown in figure 45 , figure 46 , and table 6 , the first byte of the ad5280/ad5282 is a slave address byte. it has a 7-bit slave address and an r/ w bit. the 5 msbs are 01011, and the two bits that follow are deter- mined by the state of the ad0 pin and the ad1 pin of the device. ad0 and ad1 allow the user to place up to four of the i 2 c-compatible devices on one bus. the 2-wire i 2 c serial bus protocol operates as follows. the master initiates data transfer by establishing a start condi- tion, which happens when a high-to-low transition on the sda line occurs while scl is high (see figure 45 ). the following byte is the slave address byte, which consists of the 7-bit slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is called the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master reads from the slave device. on the other hand, if the r/ w bit is low, the master writes to the slave device. a write operation contains one instruction byte more than a read operation. such an instruction byte in write mode follows the slave address byte. the most significant bit (msb) of the instruction byte labeled a /b is the rdac subaddress select. a low selects rdac1 and a high selects rdac2 for the dual channel ad5282. set a /b low for the ad5280. rs, the second msb, is the midscale reset. a logic high on this bit moves the wiper of a selected channel to the center tap where rwa = rwb. this feature effectively writes over the contents of the register and thus, when taken out of reset mode, the rdac remains at midscale. sd, the third msb, is a shutdown bit. a logic high causes the selected channel to open circuit at terminal a while shorting the wiper to terminal b. this operation yields almost 0 ?in rheostat mode or 0 v in potentiometer mode. this sd bit serves the same function as the shdn pin except that the shdn pin reacts to active low. also, the shdn pin affects both channels (ad5282) as opposed to the sd bit, which affects only the channel that is being written to. note that the shutdown operation does not disturb the contents of the register. when brought out of shutdown, the previous setting is applied to the rdac. the following two bits are o 1 and o 2 . they are extra program- mable logic outputs that can be used to drive other digital loads, logic gates, led drivers, analog switches, and so on. the three lsbs are dont care bits (see figure 45 ). after acknowledging the instruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 45 ). in read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference from write mode, where there are eight data bits followed by an acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 46 ). when all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low- to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the tenth clock pulse to establish a stop condition (see figure 45 ). in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10th clock pulse, which goes high to establish a stop condition (see figure 46 ). a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instructing the part only once. during the write cycle, each data byte updates the rdac output. for example, after the rdac has acknow- ledged its slave address and instruction bytes, the rdac output updates after these two bytes. if another byte is written to the rdac while it is still addressed to a specific slave device with the same instruction, this byte updates the output of the selected slave device. if different instructions are needed, the write mode has to start with a new slave address, instruction, and data byte again. similarly, a repeated read function of rdac is also allowed.
ad5280/ad5282 rev. b | page 17 of 28 readback rdac value the ad5280/ad5282 allow the user to read back the rdac values in read mode. however, for the dual-channel ad5282, the channel of interest is the one that is previously selected in the write mode. when users need to read the rdac values of both channels in the ad5282, they can program the first subaddress in write mode and then change to read mode to read the first channel value. after that, they can change back to write mode with the second subaddress and read the second channel value in read mode again. it is not necessary for users to issue the frame 3 data byte in write mode for subsequent readback operation. users should refer to figure 45 and figure 46 for the programming format. additional programmable logic output the ad5280/ad5282 feature addi tional programmable logic outputs, o 1 and o 2 , which can be used to drive a digital load, analog switches, and logic gates. o 1 and o 2 default to logic 0. the logic states of o 1 and o 2 can be programmed in frame 2 under write mode (see figure 45 ). these logic outputs have adequate current driving capability to sink/source milliamperes of load. users can also activate o 1 and o 2 in three ways without affecting the wiper settings by programming as follows: ? perform start, slave address, acknowledge, and instruction bytes with o 1 and o 2 specified, acknowledge, stop. ? complete the write cycle with stop, then start, slave address byte, acknowledge, instruction byte with o 1 and o 2 specified, acknowledge, stop. ? not complete the write cycle by not issuing the stop, then start, slave address byte, acknowledge, instruction byte with o 1 and o 2 specified, acknowledge, stop. self-contained shutdown function and programmable preset shutdown can be activated by strobing the shdn pin or programming the sd bit in the write mode instruction byte. as shown in figure 44 , when shutdown is asserted, the ad5280/ad5282 open sw a to let the a terminal float and short the w terminal to the b terminal. the ad5280/ad5282 consume negligible power during shutdown mode, resuming the previous setting once the shdn pin is released. in addition, shutdown can be implemented with the device digital output as shown in figure 47 . in this configuration, the device is shut down during power-up, but the user is allowed to program the device at any preset levels. when it is done, the user programs o 1 high with the valid coding and the device exits from shutdown and responds to the new setting. this self- contained shutdown function allows absolute shutdown during power-up, which is crucial in hazardous environments, without adding extra components. also, the sleep mode programming feature during shutdown allows the ad5280/ad5282 to have a programmable preset at any level, a solution that can be as effective as using other high cost eeprom devices. because of the extra power drawn on r pd , note that a high value should be chosen for the r pd . sda shdn scl r pd o 1 02929-046 figure 47. shutdown by internal logic output multiple devices on one bus figure 48 shows four ad5282 devices on the same serial bus. each has a different slave address because the states of their pin ad0 and pin ad1 are different. this allows each rdac within each device to be written to or read from independently. the master device output bus line drivers are open-drain pull- downs in a fully i 2 c-compatible interface. sd a scl r p r p 5v 5v 5v master 5 v sda ad1 ad0 ad5282 scl sda ad1 ad0 ad5282 scl sda ad1 ad0 ad5282 scl sda ad1 ad0 ad5282 scl 02929-047 figure 48. multiple ad5282 devices on one bus
ad5280/ad5282 rev. b | page 18 of 28 level shift for bidirectional interface while most old systems can be operated at one voltage, a new component can be optimized at another. when two systems operate the same signal at two different voltages, proper level shifting is needed. for instance, a 3.3 v eeprom can interface with a 5 v digital potentiometer. a level-shift scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the eeprom. figure 49 shows one of the implementations. m1 and m2 can be any n-channel signal fets or low threshold fdv301n if v dd falls below 2.5 v. r p r p r p r p g m1 m2 5v ad5282 scl2 sda2 s cl1 s da1 3.3v eeprom v dd1 = 3.3 v v dd2 = 5 v sd g sd 02929-048 figure 49. level shift for different potential operation level shift for negative voltage operation the digital potentiometer is popular in laser diode driver applications and certain telecommunications equipment level- setting applications. these applications are sometimes operated between ground and a negative supply voltage such that the systems can be biased at ground to avoid large bypass capacitors that may significantly impede the ac performance. like most digital potentiometers, the ad5280/ad5282 can be configured with a negative supply (see figure 50 ). ?5v level shifted level shifted v dd v ss gnd sda scl 02929-049 figure 50. biased at negative voltage however, the digital inputs must also be level shifted to allow proper operation because the ground is referenced to the negative potential. figure 51 shows one implementation with a few transistors and a few resistors. when v in is below the q3 threshold value, q3 is off, q1 is off, and q2 is on. in this state, v out approaches 0 v. when v in is above 2 v, q3 is on, q1 is on, and q2 is turned off. in this state, v out is pulled down to v ss . be aware that proper time shifting is also needed for successful communication with the device. + 5 v 0 q3 v dd r2 10k ? r3 10k ? v ss = ?5v v out ?5v 0 q1 q2 v in 0 0 02929-050 figure 51. level shift for bipolar potential operation esd protection all digital inputs are protected with a series input resistor and parallel zener esd structures, as shown in figure 52 . the protection applies to digital inputs sda, scl, and shdn . logic 340? v ss 02929-051 figure 52. esd protection of digital pins terminal voltage operating range the ad5280/ad5282 positive v dd and negative v ss power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. supply signals present on resistor ter mi n a l a, resistor te r mina l b, and wip er ter min a l w that exceed v dd or v ss are clamped by the internal forward- biased diodes (see figure 53 ). v dd a w b v ss 02929-053 figure 53. maximum terminal voltages set by v dd and v ss power-up sequence because there are esd protection diodes that limit the voltage compliance at terminal a, terminal b, and terminal w (see figure 53 ), it is important to power v dd /v ss before applying any voltage to the a, b, and w terminals. otherwise, the diode is forward biased such that v dd /v ss is unintentionally powered, which may affect the rest of the users circuit. the ideal power- up sequence is the following: gnd, v dd , v ss , digital inputs, and v a /v b /v w . the order of powering v a /v b /v w and digital inputs is not important as long as they are powered after v dd /v ss .
ad5280/ad5282 rev. b | page 19 of 28 layout and power supply bypassing it is a good practice to design a layout with compact, minimum lead lengths. the leads to the input should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with 0.01 f to 0.1 f disc or chip ceramic capacitors. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and filter low frequency ripple (see figure 54 ). notice that the digital ground should also be joined remotely to the analog ground at one point to minimize digital ground bounce. ad5280/ ad5282 v dd v ss v dd v ss gnd c3 10f c1 0.1f c4 10f c2 0.1f + + 02929-054 figure 54. power supply bypassing
ad5280/ad5282 rev. b | page 20 of 28 applications information bipolar dc or ac operation from dual supplies the ad5280/ad5282 can be operated from dual supplies enabling control of ground-referenced ac signals or bipolar operation. the ac signal, as high as v dd /v ss , can be applied directly across terminal a to terminal b with the output taken from terminal w. see figure 55 for a typical circuit connection. ad5282 v dd v ss sclk scl sda 2.5v p-p 5v p-p d?80 h ?5.0v +5.0v a 1 b 1 w 1 gnd mosi gnd microcontroller a 2 w 2 b 2 02929-055 figure 55. bipolar operat ion from dual supplies gain control compensation the digital potentiometer is commonly used in gain control applications such as the noninverting gain amplifier shown in figure 56 . b a w c2 4.7pf v i v o r 1 c 1 25pf 47k? 200k ? 02929-056 u1 figure 56. typical noninverting gain amplifier notice that the rdac b terminal parasitic capacitance is connected to the op amp noninverting node. it introduces a 0 for the 1/ o term with 20 db/decade (dec), whereas a typical op amp gbp has ?20 db/dec characteristics. a large r2 and finite c1 can cause the 0 frequency to fall well below the crossover frequency. thus the rate of closure becomes 40 db/dec, and the system has a 0 phase margin at the crossover frequency. the output may ring or oscillate if the input is a rectangular pulse or step function. similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input. depending on the op amp gbp, reducing the feedback resistor may extend the zeros frequency far enough to overcome the problem. a better approach is to include a compensation capacitor c2 to cancel the effect caused by c1. optimum compensation occurs when r1 c1 = r2 c2. this is not an option unless c2 is scaled as if r2 were at its maximum value. doing so may overcompensate and compromise the performance slightly when r2 is set at low values. however, it avoids the gain peaking, ringing, or oscillation at the worst case. for critical applications, c2 should be found empirically to suit the need. in general, c2 in the range of a few picofarads (pf) to no more than a few tenths of a picofarad is usually adequate for the compensation. similarly, there are w and a terminal capacitances connected to the output (not shown); fortunately, their effect at this node is less significant and the compensation can be avoided in most cases. 15 v, 8-bit i 2 c dac 02929-057 ad5280 u2 ad8512 v+ v? ad8512 v o v dd u1b v dd r bias a dr512 d1 r2 r1 b 200k ? u1a figure 57. 8-bit i 2 c dac ad5280/ad5282 can be configured as a high voltage dac, as high as 15 v. the output is )1(v2.1 256 )( 1 2 o r r d dv u (5)
ad5280/ad5282 rev. b | page 21 of 28 8-bit bipolar dac 0 2929-058 v in v out u 1 a 1 +5v ref u 2 v o a 2 u 2 ? w ?15v ?5v ref ?15v + ? op2177 + ? op2177 b rr a v 1 trim adr425 gnd ad5280 +15v +15 v figure 58. 8-bit bipolar dac figure 58 shows a low cost, 8-bit, bipolar dac. it offers the same number of adjustable steps but not the precision of conventional dacs. the linearity and temperature coefficients, especially at low value codes, are skewed by the effects of the digital potenti- ometer wiper resistance. the output of this circuit is ref o v d v ? ? ? ? ? ? ?= 1 256 2 (6) bipolar programmable gain amplifier 02929-059 u 2 u 1 a 2 v 1 a 1 b 1 w 2 a 2 a 2 w 1 a 1 v dd v dd v s8 v s8 b 2 v o r2 r1 c1 ?kvi v+ v? + ? op2177 v+ v? + ? op2177 ad5282 ad5282 figure 59. bipolar programmable gain amplifier for applications that require bipolar gain, figure 59 shows one implementation similar to the previous circuit. the digital potentiometer, u 1 , sets the adjustment range. the wiper voltage at w 2 can therefore be programmed between v i and Ckv i at a given u 2 setting. configuring a 2 in noninverting mode allows linear gain and attenuation. the transfer function is () ? ? ? ? ? ? ?+ ? ? ? ? ? ? += 1 256 1 (7) where k is the ratio of r wb1 /r wa 1 set by u 1 . as in the previous example, in the simpler and more common case where k = 1, a single digital ad5280 potentiometer is used. u 1 is replaced by a matched pair of resistors to apply v i and ?v i at the ends of the digital potentiometer. the relationship becomes i o v d2 r1 r2 v ? ? ? ? ? ? ? ? ? ? ? ? ? += 1 256 2 1 (7) if r2 is large, a compensation capacitor having a few pf may be needed to avoid any gain peaking. table 7 shows the result of adjusting d, with a2 configured as a unity gain, a gain of 2, and a gain of 10. the result is a bipolar amplifier with linearly programmable gain and a 256-step resolution. table 7. result of bipolar gain amplifier d r1 = , r2 = 0 r1 = r2 r2 = 9r1 0 ?1 ?2 ?10 64 ?0.5 ?1 ?5 128 0 0 0 192 0.5 1 5 255 0.968 1.937 9.680 programmable voltage source with boosted output for applications that require high current adjustments, such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see figure 60 ). 02929-060 c c v i 5v u 1 = ad5280 a 1 = ad8501, ad8605, ad8541 n 1 = fdv301n, 2n7002 u 1 r bias i l n 1 v o v+ v? + ? a1 a b w signal l d figure 60. programmable booster voltage source in this circuit, the inverting input of the op amp forces the v bias to be equal to the wiper voltage set by the digital potenti- ometer. the load current is then delivered by the supply via the n-channel fet n1. the n1 power handling must be adequate to dissipate (v i C v o ) i l power. this circuit can source a maximum of 100 ma with a 5 v supply. a1 needs to be a rail- to-rail input type. for precision applications, a voltage reference such as adr423 , adr292 , or ad1584 can be applied at the input of the digital potentiometer.
ad5280/ad5282 rev. b | page 22 of 28 programmable current source +5 v +5v 5v r l 100? r s 102? v+ v? ref191 gnd ad5280 op8510 u2 2 3 6 b a w c1 1f 4 u 1 0 to (2.048 + v l ) v out v in v l ?2.048v to v l i l sleep op8510 u2 02929-061 figure 61. programmable current source a programmable current source can be implemented with the circuit shown in figure 61 . ref191 is a unique, low supply headroom and high current handling precision reference that can deliver 20 ma at 2.048 v. the load current is simply the voltage across terminal b to terminal w of the digital potentiometer divided by r s . n s ref l r dv i 2 u u (8) the circuit is simple, but attention must be paid to two things. first, dual-supply op amps are ideal because the ground potential of ref191 can swing from ?2.048 v at zero scale to v l at full scale of the potentiometer setting. although the circuit works under single supply, the programmable resolution of the system is reduced. for applications that demand higher current capabilities, a few changes to the circuit in figure 61 produce an adjustable current in the range of hundreds of milliamps. first, the voltage reference needs to be replaced with a high current, low dropout regulator, such as the adp3333 , and the op amp needs to be swapped with a high current dual-supply model, such as the ad8532 . depending on the desired range of current, an appropriate value for r s must be calculated. because of the high current flowing to the load, the user must pay attention to the load impedance so as not to drive the op amp beyond the positive rail. programmable bidirectional current source a d5280 +5v r1 150k ? r2 a 14.95k ? | l r2 b 50k ? r2 i 15k ? c1 10pf r1 i 150k ? v l r l 500k ? a 2 +15v +15v a w v+ op2177 op2177 v? v+ v? a 1 ?5v ?15v ?15v 02929-062 figure 62. programmable bidirectional current source for applications that require bidirectional current control or higher voltage compliance, a howland current pump can be a solution (see figure 62 ). if the resistors are matched, the load current is w b b a l v r2 r1 r2r2 i u (9) in theory, r2 b can be made as small as needed to achieve the current needed within the a 2 output current driving capability. in this circuit, the op2177 can deliver 5 ma in either direction, and the voltage compliance approaches 15 v. it can be shown that the output impedance is b a a b o r2r2r1'r2'r1 r2r1r2'r1 z u u (10) this output impedance can be infinite if resistor r1' and resistor r2' match precisely with r1 and r2 a + r2 b , respectively. on the other hand, it can be negative if the resistors are not matched. as a result, c1 must be in the range of 1 pf to 10 pf to prevent the oscillation.
ad5280/ad5282 rev. b | page 23 of 28 programmable low-pass filter in analog-to-digital conversion applications, it is common to include an antialiasing filter to band-limit the sampling signal. dual-channel digital potentiometers can be used to construct a second-order sallen key low-pass filter (see figure 63 ). the design equations are 2 2 2 o o o i o s q s v v + + = (11) r1r2c1c2 o 1 = (12) r2c2 r1c1 q 11 += (13) users can first select some convenient values for the capacitors. to achieve maximally flat bandwidth where q = 0.707, let c1 be twice the size of c2 and let r1 = r2. as a result, r1 and r2 can be adjusted to the same settings to achieve the desirable bandwidth. v i u 1 v o r1 a r w b r2 a r w b c2 c c1 c +2.5v v+ v? ?2.5v ad8601 adjusted to same setting 02929-063 figure 63. sallen key low-pass filter programmable oscillator in a classic wien-bridge oscillator ( figure 64 ), the wien network (r, r', c, c') provides positive feedback, while r1 and r2 provide negative feedback. at the resonant frequency, f o , the overall phase shift is 0, and the positive feedback causes the circuit to oscillate. with r = r', c = c', and r2 = r2 a //(r2 b + r diode ), the oscillation frequency is rc for rc o o 2 1 1 = = (14) where r is equal to r wa such that ab r d r 256 256 ? = (15) at resonance, setting the following balances the bridge: 2 = (16) in practice, r2/r1 should be set slightly larger than 2 to ensure that oscillation can start. on the other hand, the alternate turn- on of diode d1 and diode d2 ensures that r2/r1 are smaller than 2 momentarily and, therefore, stabilizes the oscillation. once the frequency is set, the oscillation amplitude can be tuned by r2 b because dbdo vr2iv += 3 2 (17) v o , i d , and v d are interdependent variables. with proper selection of r2 b , an equilibrium is reached such that v o converges. r2 b can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to prevent saturation of the output. frequency adjustment c 2 .2n f c i 2.2nf r i 10k r 10k ba a w v+ v? b b w w d1 d2 v o u 1 vp a vn ?2.5v +2.5v r1 1k r2 b 10k r2 a 2.1k r1 = r1 i = r2b = ad5282 d1 = d2 = 1n4148 amplitude adjustment 02929-064 op1177 figure 64. programmable oscillator with amplitude control
ad5280/ad5282 rev. b | page 24 of 28 rdac circuit simulation model the internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the rdacs. configured as a potentiometer divider, the ?3 db bandwidth of the ad5280 (20 k resistor) measures 310 khz at half scale. figure 24 provides the bode plot characteristics of the three available resistor versions: 20 k, 50 k, and 200 k. a parasitic simulation model is shown in figure 65 . a macro model net list for the 20 k rdac is provided. 02929-068 c a 2 5 p f c a 2 5 p f c w 8 5 p f rdac 20k ? a b figure 65. rdac circuit simulation model for rdac = 20 k macro model net list for rdac .param d=256, rdac=20e3 * .subckt dpot (a,w,b) * ca a 0 25e-12 rwa a w {(1-d/256)*rdac+60} cw w 0 55e-12 rwb w b {d/256*rdac+60} cb b 0 25e-12 * .ends dpot
ad5280/ad5282 rev. b | page 25 of 28 outline dimensions 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 coplanarity 0.10 compliant to jedec standards mo-153-ab-1 figure 66. 14-lead thin shrink small outline package (tssop) (ru-14) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 67. 16-lead thin shrink small outline package (tssop) (ru-16) dimensions shown in millimeters
ad5280/ad5282 rev. b | page 26 of 28 ordering guide mode l 1 no. of channels r ab (k) temperature range package description package option ordering quantity ad5280bru20 1 20 ?40c to +85c 14-lead tssop ru-14 96 ad5280bru20-reel7 1 20 ?40c to +85c 14-lead tssop ru-14 1,000 ad5280bru50 1 50 ?40c to +85c 14-lead tssop ru-14 96 ad5280bru50-reel7 1 50 ?40c to +85c 14-lead tssop ru-14 1,000 ad5280bru200 1 200 ?40c to +85c 14-lead tssop ru-14 96 ad5280bru200-reel7 1 200 ?40c to +85c 14-lead tssop ru-14 1,000 ad5280bruz20 2 1 20 ?40c to +85c 14-lead tssop ru-14 96 ad5280bruz20-reel7 2 1 20 ?40c to +85c 14-lead tssop ru-14 1,000 ad5280bruz50 2 1 50 ?40c to +85c 14-lead tssop ru-14 96 ad5280bruz50-reel7 2 1 50 ?40c to +85c 14-lead tssop ru-14 1,000 ad5280bruz200 2 1 200 ?40c to +85c 14-lead tssop ru-14 96 AD5280BRUZ200-R7 2 1 200 ?40c to +85c 14-lead tssop ru-14 1,000 ad5282bru20 2 20 ?40c to +85c 16-lead tssop ru-16 96 ad5282bru20-reel7 2 20 ?40c to +85c 16-lead tssop ru-16 1,000 ad5282bru50 2 50 ?40c to +85c 16-lead tssop ru-16 96 ad5282bru50-reel7 2 50 ?40c to +85c 16-lead tssop ru-16 1,000 ad5282bru200 2 200 ?40c to +85c 16-lead tssop ru-16 96 ad5282bru200-reel7 2 200 ?40c to +85c 16-lead tssop ru-16 1,000 ad5282bruz20 2 2 20 ?40c to +85c 16-lead tssop ru-16 96 ad5282bruz20-reel7 2 2 20 ?40c to +85c 16-lead tssop ru-16 1,000 ad5282bruz50 2 2 50 ?40c to +85c 16-lead tssop ru-16 96 ad5282bruz50-reel7 2 2 50 ?40c to +85c 16-lead tssop ru-16 1,000 ad5282bruz200 2 2 200 ?40c to +85c 16-lead tssop ru-16 96 ad5282bruz200-r7 2 2 200 ?40c to +85c 16-lead tssop ru-16 1,000 ad5282-eval 2 20 evaluation board 1 line 1 contains model number, line 2 contains adi logo followed by the end-to-end resistance value, and line 3 contains date code yyww. 2 z = rohs compliant part.
ad5280/ad5282 rev. b | page 27 of 28 notes
ad5280/ad5282 rev. b | page 28 of 28 notes ?2002C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02929-0-8/07(b)

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